Barrier material and process for Cu interconnect

ABSTRACT

A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods.

TECHNICAL FIELD

This invention relates generally to semiconductor device fabrication andmore particularly to a structure and method for improved resistance toelectromigration problems with conductive lines and vias, such ascopper, between interconnected layers.

BACKGROUND

In modern integrated circuits, minimum feature sizes, such as thechannel length of field effect transistors, have reached the deepsub-micron range, thereby steadily increasing performance of thesecircuits in terms of speed and power consumption. As the size of theindividual circuit elements is reduced, so is the available real estatefor conductive interconnects in integrated circuits. Consequently, theseinterconnects have to be reduced to compensate for a reduced amount ofavailable real estate and for an increased number of circuit elementsprovided per chip.

In integrated circuits having minimum dimensions of approximately 0.35μm and less, a limiting factor of device performance is the signalpropagation delay caused by the switching speed of the transistorelements. As the channel length of these transistor elements has nowreached 0.18 μm and less, however, capacitance between neighboringconductive structures is increasingly problematic. Parasitic RC timeconstants therefore require the introduction of a new materials andmethods for forming metallization layers.

Traditionally, metallization layers are formed by a dielectric layerstack including, for example, silicon dioxide and/or silicon nitridewith aluminum as the typical metal. Since aluminum exhibits significantelectromigration at higher current densities, copper is replacingaluminum. Copper has significantly lower electrical resistance andreduced electromigration problems.

The introduction of copper, however, entails a plurality of issues to bedealt with. For example, copper may not be deposited in higher amountsin an efficient manner by well-established deposition methods, such aschemical and physical vapor deposition. Moreover, copper may not beefficiently patterned by well-established anisotropic etch processes andtherefore the so-called damascene technique is employed in formingmetallization layers including copper lines. Typically, in the damascenetechnique, the dielectric layer is deposited and then patterned withtrenches and vias that are subsequently filled with copper by platingmethods, such as electroplating or electroless plating.

A further issue is the ability of copper to readily diffuse in silicondioxide. Therefore, copper diffusion may negatively affect deviceperformance, or may even lead to a complete failure of the device. It istherefore necessary to provide a diffusion barrier layer between thecopper surfaces and the neighboring materials to substantially preventcopper from migrating to sensitive device regions. Silicon nitride isknown as an effective copper diffusion barrier, and is thus frequentlyused as a dielectric barrier material separating a copper surface froman interlayer dielectric, such as silicon dioxide.

Although copper exhibits superior characteristics with respect toresistance to electromigration compared to aluminum, the ongoingshrinkage of feature sizes, however, leads to increased currentdensities, thereby causing a non-acceptable degree of electromigration.Electromigration is a diffusion phenomenon occurring under the influenceof an electric field, which leads to copper diffusion in the directionof the moving charge carriers. This can produce voids in the copperlines that may cause device failure. It has been confirmed that thesevoids typically originate at the copper silicon nitride interface andrepresent one of the most dominant diffusion paths in coppermetallization structures. It is therefore of great importance to producehigh quality interfaces between the copper and the diffusion barrierlayer to reduce the electromigration to an acceptable degree.

As previously noted, the device performance of extremely scaledintegrated circuits is substantially limited by the parasiticcapacitances of adjacent interconnect lines, which may be reduced bydecreasing the resistivity thereof and by decreasing the capacitivecoupling in that the overall dielectric constant of the dielectric layeris maintained as low as possible. Since silicon nitride has a relativelyhigh dielectric constant k of approximately 7 compared to silicondioxide (k≈4) or other silicon dioxide based low-k dielectric layers(k<4), it is generally preferable to form the silicon nitride layer witha minimum thickness. It turns out, however, that the barriercharacteristics of the silicon nitride layer depend on the thicknessthereof so that thinning the silicon nitride layer, as would bedesirable for a reduced overall dielectric constant, may not bepractical to an extent as required for further scaling semiconductordevices including copper metallization layers without compromisingdevice performance.

In light of the above-specified problems, a need exists for diffusionbarrier layers exhibiting an improvement with respect to diffusionbarrier efficiency, resistance to electromigration, lower parasiticcapacitance, and other problems.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, andtechnical advantages are generally achieved, by preferred embodiments ofthe present invention, in which improved structures and methods relatingto copper diffusion barriers yield devices having enhancedelectromigration performance.

In a preferred embodiment, a semiconductor device comprises a substrateand a dielectric layer on the substrate. The dielectric layer has atleast one opening. The dielectric layer, if porous, may optionallyundergo a pore-sealing process thereby improving its dielectriccharacteristics. A diffusion barrier layer is deposited on thedielectric layer. A conductor, preferably copper, is deposited over thebarrier. An optional glue layer is deposited between the barrier layerand the conductor.

In an alternative preferred embodiment, the thickness ratio of the gluelayer to the barrier layer is about 1 to 50. Another alternativeembodiment comprises treating the barrier with an electron beam or anRTP process to improve properties such as adhesion and conductivity.

In other preferred embodiments, the barrier layer comprises a layerabout 10 to 30 Angstroms thick. The barrier layer includes of at leastone layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, andcombinations thereof. The barrier layer may be applied using physicalvapor deposition (PVD), chemical vapor deposition (CVD), plasma enhancedchemical vapor deposition (PECVD), or plasma enhanced atomic layerdeposition (PEALD).

In other preferred embodiments, the glue layer comprises a metal-richnitride about 10 to 500 Angstroms thick. It is applied using PVD, CVD,PECVD, PEALD, or preferably ALD. Alternative preferred embodiments mayinclude a glue layer comprising at least one layer of Ru, Ta, Ti, W, Co,Ni, Al, Nb, AlCu, and combinations thereof.

Still other preferred embodiments may further include a cap layerdeposited at least upon the conductor. It may be deposited by ALD, PVD,PECVD, PEALD, and/or CVD methods, including nitridation and silicidationmethods. The cap layer preferably includes at least one layer of Co, W,Al, Ta, Ti, Ni, or Ru, and combinations thereof.

Other alternative preferred embodiments further include a conductorannealing step. Preferably, the annealing step is performed at about 150to 450° C., for about 0.5 to 5 minutes, in N2/H2 forming gas.

Additional features and advantages of embodiments of the invention willbe described hereinafter, which form the subject of the claims of theinvention. It should be appreciated by those skilled in the art that thespecific embodiments disclosed might be readily utilized as a basis formodifying or designing other structures or processes for carrying outthe purposes of the present invention. It should also be realized bythose skilled in the art that such equivalent constructions andvariations on the example embodiments described do not depart from thespirit and scope of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross sectional view of a semiconductor device at anintermediate step in an exemplary damascene process further illustratinga barrier layer according to preferred embodiments;

FIG. 2 is a cross-sectional view showing a preferred embodiment thatincludes barrier, glue, and seed layers;

FIG. 3 is a cross-sectional view showing a conductor deposited on theglue layer according to preferred embodiments;

FIG. 4 is a cross-sectional view showing CMP planarization according topreferred embodiments;

FIG. 5 cross-sectional view showing a cap layer according to preferredembodiments; and

FIG. 6 is a process flow diagram according to several embodiments of thepresent invention.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the preferredembodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The operation and fabrication of the presently preferred embodiments arediscussed in detail below. However, the embodiments and examplesdescribed herein are not the only applications or uses contemplated forthe invention. The specific embodiments discussed are merelyillustrative of specific ways to make and use the invention, and do notlimit the scope of the invention or the appended claims.

This invention relates generally to semiconductor device fabrication andmore particularly to a structure and method for improved resistance toelectromigration problems with conductive lines and vias, such ascopper, between interconnected layers. The present invention will now bedescribed with respect to preferred embodiments in a specific context,namely the creation of copper conductive lines and vias in the damasceneprocess. It is believed that embodiments of this invention areparticularly advantageous when used in this process. It is furtherbelieved that embodiments of this invention are advantageous when usedin other semiconductor fabrication applications wherein diffusionbarriers and electromigration, for example, are a concern. It is furtherbelieved that embodiments described herein will benefit other integratedcircuit interconnection applications not specifically mentioned.Therefore, the specific embodiments discussed are merely illustrative ofspecific ways to make and use the invention, and do not limit the scopeof the invention.

Referring now to FIG. 1, there is shown a cross section of therepresentative intermediate damascene structure 100 created in thesurface of a semiconductor substrate 102 that is to be treated inaccordance with an exemplary damascene process and embodiments of theinvention. The substrate 102 may comprise, for example, functional andlogical devices, or it may comprise other interconnected layers. Thedetails of the damascene process are described by Bao et al. in U.S.Pat. No. 6,248,665 and in U.S. patent publication 2004/0121583, both ofwhich are hereby incorporated by reference.

Referring to FIG. 1, in an exemplary application of the presentinvention, there is shown a cross sectional, side view representation ofa portion of a semiconductor device having a semiconductor wafer with ananisotropically etched, intermediate, dual damascene structure 100.Within the intermediate damascene structure 100 is a recessed feature 85having a via portion 104 and an overlying trench line portion 106. Whilethere are several ways to form a dual damascene structure, one approachinvolves at least two photolithographic patterning and anisotropicetching steps to first form via openings 104 followed by a similarprocess to form overlying trench line openings 106 encompassing one ormore via openings 104.

Still referring to FIG. 1, a first etch stop layer 103, formed of, forexample silicon nitride (Si3N4), is provided over a conductive region108, for example a copper damascene structure formed in an underlyingdielectric insulating layer 110. In accordance with the conventionaldamascene process, the word copper is known to include suitable copperalloys. Overlying the first etch stop layer 103 is another insulatingdielectric layer 112, also referred to as an inter-metal dielectric(IMD) layer.

For example, the IMD layer 112 is a low-k (i.e. k less than about 4)dielectric, for example a carbon doped silicon dioxide, also referred toas organo silicate glass (OSG) and C-oxide. In alternative embodiments,low-k materials may include borophosphosilicate glass (BPSG),borosilicate glass (BSG), phosphosilicate glass (PSG), deposited overthe surface of the semiconductor structures to a thickness of betweenabout 5000 to 9000 Angstroms and preferably planarized. Exemplaryorganic low-k materials include polyarylene ether, hydrogensilesquioxane (HSQ), methyl silsesquioxane (MSQ), polysilsequioxane,polyimide, benzocyclbbutene, and amorphous Teflon. Other types of low-kmaterials suitably used with the method of the present invention includefluorinated silicate glass (FSG) and porous oxides. In preferredembodiments, the dielectric layer is preferably a low-k materialcontaining C, O, Si, and F, such as fluorine-doped —(O—Si(CH3)2—O)—.

Open pores in low-k materials, e.g. IMD layer 112, are known to degradeperformance. Therefore embodiments include a pore-sealing methodcomprising plasma pore sealing using Ar and NH3, e-beam pore sealing,metal organic pore sealing, or preferably vapor pore sealing. Inpreferred embodiments, a low-k surface is subjected to treatment with4MS (tetramethylsilane) at a temperature of about 400° C. The 4MS usedin the treatment of the present invention can be replaced bytrimethylsilane, dimethylsilane or methylsilane. The vapor can becomposed of organic or metal-organic molecules, preferably having a sizelarger than 10 Å. The temperature ranges from about 350-450° C. forabout 5-30 seconds.

The e-beam pore sealing employs an electron beam with a typicalcondition of 2000˜5000 keV, 1˜6 mA, and 75˜100 μC/cm2. Plasma poresealing uses an Ar plasma to bombard the low-k surface to block thepores of the sidewall of the dual damascene.

Still referring to FIG. 1, overlying the IMD layer 112 is formed an IMDcovering dielectric layer, for example an etch stop layer 114. The etchstop layer 114 may include, for example, silicon nitride and/or siliconoxynitride (SiON), which may function as both an etching stop andanti-reflectance coating (ARC) layer. The etch stop layer 114 ispreferably from about 500 Angstroms to about 1500 Angstroms inthickness.

The dual damascene structure 100 is formed by first sequentiallyphotolithographically patterning and anisotropically etching the viaopening 104 through the etch stop layer 114, the IMD layer 112, and atleast partially through the first etch stop layer 103. This is followedby a similar process to photolithographically pattern andanisotropically etch a trench opening 106 through the etch stop layer114 and a portion of the IMD layer 112. These steps form a trenchopening 106 overlying and encompassing the via opening 104. It will beappreciated that the trench opening 106 may encompass one or more viaopenings 104 and that the trench opening 106 and via opening 104 may beformed in separate stacked IMD layers 112 including another etch stoplayer 114 formed between the respective IMD layers.

Still referring to FIG. 1, a barrier layer 116 is blanket deposited toline at least the dual damascene feature opening. The barrier layer ispreferably about 10 to 30 Angstroms thick, and it forms a barrier for Cudiffusion. The barrier layer 116 may include a metal nitride such asTaN, TiN, WN, ThN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinationsthereof. In alternative embodiments the barrier layer 116 is metal rich,either throughout the bulk or only on the surface. In metal-rich,barrier layers, the ratio of nitrogen to metal is preferably less thanabout one (atomic ratio).

In alternative preferred embodiments, the barrier layer includes a firstbarrier layer on the surface of the low-k dielectric layer and a secondbarrier layer on the first barrier layer. The first barrier layerincludes an atomic layer deposited (ALD) material selected from thegroup consisting essentially of Ta, W, and combinations thereof. Thesecond barrier layer is selected from the group consisting essentiallyof Ni, Co, Al, AlCu alloy, W, Ti, Ta, Ra, Ru, and combinations thereof.An optional Cu seed layer may be deposited on the second barrier layer.

The barrier layer 116 may be applied using physical vapor deposition(PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), or plasma enhanced atomic layer deposition (PEALD).In preferred embodiments, the barrier layer 116 comprises TaN, and it isdeposited using atomic layer deposition (ALD).

An ALD deposited, TaN barrier layer 116 is particularly advantageous informing a damascene structure with reduced capacitance and reducedelectromigration effects. As semiconductor dimensions continue toshrink, capacitance between conductive structures is increasinglyproblematic. Applicants have found that ALD barrier 116 deposition ismore preferred than, for example, PVD. In the preferred embodimentcomprising a TaN barrier 116, for example, applicants found that ALDsignificantly reduces the parasitic capacitance between neighboringconductive structures by as much as 11.5%, as compared to PVD. An ALDdeposited barrier, therefore, enables thinner metal lines because themetal line with ALD barrier has a lower effective resisitvity.

In still other embodiments, the barrier layer 116 includes a Ta/TaNbi-layer structure. Ta/TaN bilayer embodiments include: PEALD TaN andALD Ta, ALD TaN and PEALD Ta, or PEALD TaN and PEALD Ta.

As shown in FIG. 2, preferred embodiments contain a glue layer 118between the barrier layer 116 and an overlaying conductor (describedbelow, see FIG. 3, 120). Glue layer 118 enhances adhesion between andadjacent layers. The glue layer 118 preferably contains materials thatbond with copper and/or the underlying barrier layer. It may be about 10to 500 Angstroms thick, preferably less than about 150 Å. It is alsopreferably metal-rich.

In alternative embodiments, the glue layer 118 preferably comprises twolayers (not specifically shown). The first layer is preferably ametal-rich thin layer from about 130 to 170 Angstroms, preferably about150 Angstroms. The second layer is stoichiometric metal nitride layerabout 500 to 600 Angstroms, preferably about 550 Angstroms. The gluelayer 118 may be applied using PVD, CVD, PECVD, PEALD, and, preferably,ALD at a deposition rate less than about lA/sec at about 100-300° C.

Alternative embodiments include a glue layer 118 consisting of Ru, Ta,Ti, W, Co, Ni, Al, Nb, AlCu alloy, and combinations thereof. Inpreferred embodiments, the ratio of the glue layer 118 thickness to thebarrier layer 116 thickness is about 1 to 50.

Prior to deposition of a conductor, a seed layer 119 is optionallydeposited over the glue layer 118 by, for example, PVD and/or CVD. Seedlayer 119, preferably copper, is PVD deposited to form a continuouslayer about 400 to 700 Å thick over the wafer process surface, therebyproviding a continuously conductive surface for forming the bulk of thecopper during the ECD process.

Still referring to FIG. 2, the embodiment summarized therein ispreferably annealed at about 300° C. for about 1 minute. Annealingadvantageously lowers the effective resistivity of the barrier/glue/seedstack. Typically glue layers that include Ta and Co exhibit the mostimprovement.

In other embodiments of the present invention, there is an alternativemethod to improve adhesion between the barrier layer and adjacentlayers. The deposition of the barrier layer, as described above, mayfurther include a thermal treatment such as electron beam annealing orrapid thermal processing, RTP. Preferred treatments advantageouslyenhance wetability and/or adhesion between the barrier layer and thecopper layer.

The thermal adhesion process is preferably performed at an intermediatestage during the ALD deposition of the barrier. Typically, barrierformation such as ALD TaN includes multiple steps. First, a Ta precursoris used to form a saturated surface layer. Next, the saturated surfacelayer is reduced and nitrided using NH3 to form a Ta_(x)N_(y) monolayer.The thermal adhesion treatment occurs between these two steps. In thecase of a WCN barrier, which is a three-step deposition process, thethermal adhesion is performed prior to the reduction step. The RTP maybe incorporated into the ALD chamber. A typical RTP temperature is about200 to 400° C.

Referring to FIG. 3, following deposition of glue layer 118, a conductor120, preferably copper, is electroplated according to a conventionalelectro-chemical deposition (ECD) process to fill the dual damascenetrench 106 and via 104 including an overlying portion above the trenchlevel. In alternative embodiments, a seed layer (not shown) is betweenglue layer 118 and conductor 120. Although other copper filling methods,such as PVD and CVD, may be used, electroplating (electrodeposition) ispreferred because of its superior gap-filling and step coverage.Alternative embodiments may include the conductor 120 comprising atleast one of Cu, Al, Au, or Ag, and combinations thereof, or alloyedcompositions thereof.

A chemical mechanical polishing (CMP) may be used to polish theconductor fill to the level of the feature. In another alternative,electropolishing or overburden reduction may be used in place of CMP orserially with CMP. In the alternative, a simultaneous CMP and platingprocess may be performed. As shown in FIG. 4, the CMP process forms arecessed area 121 due to preferential removal of the softer conductor120.

Referring still to FIG. 4, in another embodiment, an upper portion 122of the recessed conductor is removed. The depth of the recessed area 121is increased by first oxidizing the upper portion 122 of the exposedconductor, e.g. copper, followed by another CMP step or wet etching stepto remove the oxidized upper portion 122 of the copper feature.

Following CMP planarization, alternative preferred embodiments include aseed layer (not shown) and conductor 120 anneal. Preferably, theannealing step is performed at about 150 to 450° C., for about 0.5 to 5minutes, in N₂/H₂ forming gas. The anneal causes metals in the seedlayer to migrate or diffuse throughout the copper fill layer (120),thereby forming a copper-metal fill layer (120). Preferably, the Cu seedlayer includes titanium. Annealing advantageously causes the Ti todistribute approximately uniformly within conductor layer 120 and form auniform copper-titanium fill layer (120). The anneal also causesgranularity of the surface of the conductor layer 120 and results inimproved adhesion between the conductor layer 120 and a cap layer (asshown in FIG. 5) that is deposited over this surface.

Referring to FIG. 5, in an embodiment of the present invention,following the CMP, a cap layer 124 is deposited over the damascenestructure. The cap layer 124 is preferably deposited to a thickness ofabout 50 Angstroms to about 500 Angstroms. The cap layer 124 ispreferably sufficiently thick to avoid copper diffusion. It is depositedby conventional ALD, PVD, PECVD, PEALD, and/or CVD methods, includingnitridation and silicidation methods known in the art. The cap layer 124preferably includes at least one layer of W, Al, Ta, Ti, Ni, Ru, ornitrides thereof. Preferred embodiments include a Co or nitride-Co caplayer deposited by CVD or ALD.

Still other embodiments may include a cap layer comprising at least onelayer of a carbon-containing dielectric (such as SiC, SiOC, SiCN), anitrogen-containing dielectric, a nitrogen-containing conductive layer,or a silicon-containing layer.

Returning to FIG. 5, following the CMP and capping processes, an etchstop layer 126 of silicon nitride may be deposited over the processwafer surface including over the barrier capping layer overlying thecopper feature.

Referring now to FIG. 6, there is shown a process flow diagram includingseveral of the preferred embodiments of the present invention. Inprocess 602, a substrate is provided, and within the substrate a featureopening is formed in a low-k dielectric insulating layer (ILD). Inprocess 604, the pores of the low-k dielectric are sealed. In process605, the feature opening is lined with a metal nitride barrier layer. Inprocess 606, the barrier layer is treated to enhance adhesion. Inprocess 608, a metal-rich nitride glue layer is applied. In process 610,a Cu seed layer is applied. In process 612, the feature opening isfilled with a conductor. In process 614, the structure is CMPplanarized. In process 616, the conductor is annealed. In process 618, acap layer is applied.

The embodiments of the invention described above are exemplary and notlimiting, and variations that are apparent to those skilled in the artthat include the features of the invention are within the scope of theinvention and the appended claims. Although embodiments of the presentinvention and their advantages have been described in detail, it shouldbe understood that various changes, substitutions and alterations can bemade herein without departing from the spirit and scope of the inventionas defined by the appended claims.

For example, it will be readily understood by those skilled in the artthat many of the features, functions, processes, and materials describedherein may be varied while remaining within the scope of the presentinvention. Moreover, the scope of the present application is notintended to be limited to the particular embodiments of the process,machine, manufacture, composition of matter, means, methods and stepsdescribed in the specification. As one of ordinary skill in the art willreadily appreciate from the disclosure of the present invention,processes, machines, manufacture, compositions of matter, means,methods, or steps, presently existing or later to be developed, thatperform substantially the same function or achieve substantially thesame result as the corresponding embodiments described herein may beutilized according to the present invention. Accordingly, the appendedclaims are intended to include within their scope such processes,machines, manufacture, compositions of matter, means, methods, or steps.

1. A semiconductor device having enhanced electromigration performance,the device comprising: a low-k dielectric layer, the low-k dielectriclayer having a surface with a recessed feature; a diffusion barrierlayer on the surface of the low-k dielectric layer; a glue layer on thediffusion barrier layer; and a conductor on the glue layer, theconductor filling the recessed feature.
 2. The semiconductor device ofclaim 1, further including a cap layer on the conductor, wherein the caplayer is selected from the group consisting essentially of Co, W, Al,Ta, Ti, Ni, Ru, and combinations thereof.
 3. The semiconductor device ofclaim 1, wherein the diffusion barrier layer includes a first barrierlayer on the surface of the low-k dielectric layer and a second barrierlayer on the first barrier layer.
 4. The semiconductor device of claim3, wherein the first barrier layer is selected from the group consistingessentially of Ta, W, and combinations thereof.
 5. The semiconductordevice of claim 3, wherein the second barrier layer is selected from thegroup consisting essentially of Ni, Co, Al, AlCu alloy, W, Ti, Ta, Ra,Ru, and combinations thereof.
 6. The semiconductor device of claim 3,wherein the second barrier layer is selected from the group consistingessentially of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN,and combinations thereof.
 7. The semiconductor device of claim 1,wherein the diffusion barrier layer is selected from the groupconsisting essentially of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN,NbN, AlN, and combinations thereof.
 8. The semiconductor device of claim7, wherein the diffusion barrier layer is metal rich.
 9. Thesemiconductor device of claim 7, wherein the diffusion barrier layerfurther includes a metal rich surface.
 10. The semiconductor device ofclaim 7, wherein the diffusion barrier layer further includes a thermaltreatment to enhance adhesion.
 11. The semiconductor device of claim 1,wherein the diffusion barrier layer is about 10 to 30 Angstroms.
 12. Thesemiconductor device of claim 1, wherein the low-k dielectric layercomprises C, O, Si, and F.
 13. The semiconductor device of claim 2,wherein the cap layer is selected from the group consisting essentiallyof a carbon-containing dielectric, a nitrogen-containing dielectric, anitrogen-containing conductor, a silicon-containing conductive layer,and silicon, and combinations thereof.
 14. The semiconductor device ofclaim 1, wherein the glue layer is selected from the group consistingessentially of a metal-rich nitride, Ru, Ta, Ti, W, Co, Ni, Al, Nb,AlCu, and combinations thereof.
 15. The semiconductor device of claim14, wherein a thickness ratio of the glue layer to the diffusion barrierlayer is about 1 to
 50. 16. The semiconductor device of claim 14,wherein a thickness of the glue layer is about 10 to 500 Angstroms. 17.The semiconductor device of claim 14, wherein the metal-rich nitridecomprises TaN and wherein an atomic ratio of nitrogen to tantalum isless than about
 1. 18. The semiconductor device of claim 1, wherein theconductor is selected from the group consisting essentially of Cu, Al,Au, and Ag, and combinations thereof.
 19. A method of reducingelectromigration effects in a copper damascene device, the methodcomprising: forming a low-k dielectric layer, the low-k dielectric layerhaving a surface with a recessed feature; forming a diffusion barrierlayer over the surface of the low-k dielectric layer; forming a gluelayer upon the diffusion barrier layer; filing the recessed feature witha conductor; annealing the conductor; and forming a cap layer upon theconductor.
 20. The method of claim 19, wherein the cap layer is selectedfrom the group consisting essentially of Co, W, Al, Ta, Ti, Ni, Ru, andcombinations thereof.
 21. The method of claim 19, wherein the diffusionbarrier layer is selected from the group consisting essentially of TaN,TiN, WN, ThN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinationsthereof.
 22. The method of claim 19, wherein the diffusion barrier layeris about 10 to 30 Angstroms.
 23. The method of claim 19, wherein the caplayer is selected from the group consisting essentially of acarbon-containing dielectric, a nitrogen-containing dielectric, anitrogen-containing conductor, a silicon-containing conductive layer,and silicon, and combinations thereof.
 24. The method of claim 19,further including thermally treating the diffusion barrier layer. 25.The method of claim 19, wherein the glue layer is selected from thegroup consisting essentially of a metal-rich nitride, Ru, Ta, Ti, W, Co,Ni, Al, Nb, AlCu, and combinations thereof.
 26. The method of claim 25,wherein the glue layer is deposited using physical vapor deposition(PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), or plasma enhanced atomic layer deposition (PEALD).27. The method of claim 25, wherein a thickness ratio of the glue layerto the diffusion barrier layer is about 1 to
 50. 28. The method of claim25, wherein a thickness of the glue layer is about 10 to 500 Angstroms.29. The method claim 25, wherein the metal-rich nitride comprises TaNand wherein an atomic ratio of nitrogen to tantalum is less thanabout
 1. 30. The method of claim 19, wherein the conductor annealingstep comprises annealing at about 150 to 450° C. for about 0.5 to 5minutes in forming gas.
 31. The method of claim 19, wherein thediffusion barrier layer is deposited using physical vapor deposition(PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), or plasma enhanced atomic layer deposition (PEALD).32. The method of claim 19, wherein the cap layer is deposited usingphysical vapor deposition (PVD), chemical vapor deposition (CVD), plasmaenhanced chemical vapor deposition (PECVD), or plasma enhanced atomiclayer deposition (PEALD).
 33. A method for forming a semiconductordevice, comprising: providing a substrate, the substrate including alow-k dielectric layer with an opening; performing a pore sealingprocess; forming a barrier layer within the opening; forming a gluelayer on the barrier layer; forming a seed layer on the glue layer;forming a conductor on the seed layer; and forming a cap layer on theconductor.
 34. The method of claim 33, wherein the cap layer is selectedfrom the group consisting essentially of Co, W, Al, Ta, Ti, Ni, Ru, andcombinations thereof.
 35. The method of claim 33, wherein the barrierlayer is selected from the group consisting essentially of TaN, TiN, WN,ThN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. 36.The method of claim 33, wherein the barrier layer is about 10 to 30Angstroms.
 37. The method of claim 33, wherein the cap layer is selectedfrom the group consisting essentially of a carbon-containing dielectric,a nitrogen-containing dielectric, a nitrogen-containing conductor, asilicon-containing conductive layer, and silicon, and combinationsthereof.
 38. The method of claim 33, wherein the glue layer is selectedfrom the group consisting essentially of a metal-rich nitride, Ru, Ta,Ti, W, Co, Ni, Al, Nb, AlCu, and combinations thereof.
 39. The method ofclaim 33, wherein a thickness ratio of the glue layer to the barrierlayer is about 1 to
 50. 40. The method of claim 33, wherein a thicknessof the glue layer is about 10 to 500 Angstroms.
 41. The method claim 38,wherein the metal-rich nitride comprises TaN and wherein an atomic ratioof nitrogen to tantalum is less than about
 1. 42. The method of claim33, further comprising annealing the conductor at about 150 to 450° C.for about 0.5 to 5 minutes in forming gas.
 43. The method of claim 33,wherein the pore sealing process comprises vapor pore sealing.